A standard multiplexor (MUX) circuit is used to select one signal from multiple signals. More specifically, a standard MUX circuit can be implemented on an integrated circuit (IC) and used to select data from a particular one of a plurality of data connections.
For example, a MUX circuit within an IC may comprise eight data connections that transmit 128-bit data words. Typically, each of the 128-bit data words may be routed to multiplexor logic on the IC via a connection that comprises 128 routing wires, e.g., a wire for each bit that is transmitted. Therefore, in this particular example, 1024 routing wires on the IC would be used to route eight data words from eight data connections to the multiplexor logic. The multiplexor logic selects and outputs one of the 128 bit words received by the multiplexor logic. Notably, the aforedescribed MUX circuit is prone to routing congestion and the inherent problems associated therewith, e.g., difficulty in designing and fabricating.
A conventional MUX circuit 100 is depicted in FIG. 1. The MUX circuit 100, of FIG. 1 comprises an array of data connections 102-105 (e.g. data ports, etc.) and multiplexor logic 110. During operation, each data connection 102-105 transmits a 128-bit data word to multiplexor logic 110 via 128-bit wide data connections 112-115, respectively.
The multiplexor logic 110 receives the data words and, at any given time, selects one of the data words on one of the connections 112-115 based on a control signal from MUX control logic 109. The MUX logic 110 transmits the selected data word via an output connection 126, to an IC component, such as a system bus 124. The MUX design depicted by FIG. 1 employs a significant number of routing wires, and the number of routing wires increases as the number of data connections increases.
In the past, dynamic MUXs and tristate MUXs have been employed in an attempt to address routing congestion caused by large numbers of routing wires. However, a dynamic MUX typically requires more power, has smaller noise margins, and takes more time to design correctly. Further, usage of tristate multiplexors is sometimes acceptable when the distances between the data connections 102-105 and the multiplexor logic 110 are small. However, speed and noise degradation typically increases as the distances between the data connections increase.